Multiple patterning is a common patterning technique in the semiconductor chip manufacturing industry. Multiple patterning enables chipmakers to image integrated circuit (IC) designs at 20 nanometers (nm) and below. For 10 nm technology, double patterning is commonly used and typically refers to a litho-etch-litho-etch (LELE) pitch-splitting process or a spacer technique called self-aligned double patterning (SADP). However, in the case of 7 nm technology and below, patterning techniques other than extreme ultraviolet (EUV) lithography require triple or even quadruple patterning. These patterning processes can include litho-etch-litho-etch-litho-etch (LELELE) or self-aligned quadruple patterning (SAQP). During such multiple patterning techniques, patterns which are formed earlier are exposed to subsequent patterning steps, such as rework, which typically introduce changes in the critical dimension (CD) or profile of the earlier formed features.